1. Field of the Invention
This invention is related to the field of microprocessors, and more particularly, to processing microcoded instructions within a microprocessor.
2. Description of the Related Art
Instructions processed in a microprocessor are encoded as a sequence of ones and zeros. For some processor architectures, instructions may be encoded with a fixed length, such as a certain number of bytes. For other architectures, such as the x86 architecture, the length of instructions may vary. The x86 microprocessor architecture specifies a variable length instruction set (i.e., an instruction set in which various instructions are each specified by differing numbers of bytes). For example, the 80386 and later versions of x86 microprocessors employ between 1 and 15 bytes to specify a particular instruction. Instructions have an opcode, which may be 1-2 bytes, and additional bytes may be added to specify addressing modes, operands, and additional details regarding the instruction to be executed. The x86 microprocessor architecture is one example of an architecture having complex instructions that may be implemented in microcode.
Certain instructions within the x86 instruction set are quite complex, specifying multiple operations to be performed. For example, the PUSHA instruction specifies that eight general purpose x86 registers be pushed onto a stack defined by the value in the ESP register. Thus, a PUSHA instruction specifies that a store operation be performed for each register and the ESP register may be decremented between each store operation to generate the address for the next store operation.
Less complex instructions are typically directly decoded by hardware decode units within the microprocessor. The terms “directly-decoded instruction” or “fastpath instruction” or “non-complex instruction” may be used interchangeably herein to refer to an instruction that is decoded and executed by the microprocessor without the aid of a microcode instruction unit. Directly-decoded instructions are decoded into component operations via hardware decode, without the intervention of a microcode instruction unit, and then these operations are executed by functional units included within the microprocessor.
Often, long running or complex instructions are classified as microcoded instructions. Microcoded instructions are handled by a microcode instruction unit within the microprocessor, which decodes the complex microcoded instruction and produces a series of less-complex operations for execution by the microprocessor. These simpler operations corresponding to the microcoded instruction are typically stored in a read-only memory (ROM) within the microcode unit. Thus, microcoded instructions are often referred to as MROM instructions.
A microprocessor may decode or partially decode an instruction encoding to determine if an instruction is a fastpath instruction or an MROM instruction. The process of determining the address in a microcode ROM to begin execution of a microcode routine to implement an MROM instruction is referred to as microcode entry point generation. If the instruction is an MROM instruction, the microprocessor's microcode instruction unit determines the entry point address within the microprocessor's microcode ROM at which the first of the corresponding microcode operations (collectively referred to as a microcode routine) are stored. The microcode routines to implement MROM instructions are typically stored in a sequentially addressed ROM. Typically, the microcode instruction unit maps or translates some or all of the instruction encoding to a microcode entry point ROM address for a location in the microcode ROM at which the corresponding microcode routine begins. This mapping may be performed by a lookup table, content-addressable memory, combinatorial logic or any other mechanism for translating the MROM instruction encoding to a ROM address. For example, microcode may be stored in a 3K ROM. The microcode unit may map an MROM instruction encoding to any 12-bit ROM address in the range 0x000-0xBFF according to where the entry point of the microcode routine for that MROM instruction is located. This ROM address is sent to an address decoder for the ROM that selects the addressed ROM entry. The microcode operation at the selected ROM entry is transferred out of the ROM into execution. The ROM address may be incremented to the next microcode operation in the routine or the next address may be contained within the operation, giving a threaded form of storage. Also, some microcode operations may indicate a jump to a non-sequential address in the microcode ROM. Multiple clock cycles may be used to transfer into execution the entire set of microcode operations within the ROM that correspond to the MROM instruction.
Once the microcode operations are output from the MROM unit, these operations are typically included within the operation stream that is dispatched to one or more devices that schedule operations for execution. Thus, typical MROM units, in effect, perform instruction expansion on the microcoded instruction.